# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32_PIC
--- |

  define i32 @mod4_0_to_11(i32 %a) {
  entry:
    switch i32 %a, label %sw.default [
      i32 0, label %sw.bb
      i32 4, label %sw.bb
      i32 1, label %sw.bb1
      i32 5, label %sw.bb1
      i32 2, label %sw.bb2
      i32 6, label %sw.bb2
      i32 3, label %sw.bb3
      i32 7, label %sw.bb3
    ]

  sw.bb:                                            ; preds = %entry, %entry
    ret i32 0

  sw.bb1:                                           ; preds = %entry, %entry
    ret i32 1

  sw.bb2:                                           ; preds = %entry, %entry
    ret i32 2

  sw.bb3:                                           ; preds = %entry, %entry
    ret i32 3

  sw.default:                                       ; preds = %entry
    br label %sw.epilog

  sw.epilog:                                        ; preds = %sw.default
    switch i32 %a, label %sw.default8 [
      i32 8, label %sw.bb4
      i32 9, label %sw.bb5
      i32 10, label %sw.bb6
      i32 11, label %sw.bb7
    ]

  sw.bb4:                                           ; preds = %sw.epilog
    ret i32 0

  sw.bb5:                                           ; preds = %sw.epilog
    ret i32 1

  sw.bb6:                                           ; preds = %sw.epilog
    ret i32 2

  sw.bb7:                                           ; preds = %sw.epilog
    ret i32 3

  sw.default8:                                      ; preds = %sw.epilog
    ret i32 -1
  }

...
---
name:            mod4_0_to_11
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
jumpTable:
  kind:            block-address
  entries:
    - id:              0
      blocks:          [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.2', '%bb.3',
                         '%bb.4', '%bb.5' ]
    - id:              1
      blocks:          [ '%bb.8', '%bb.9', '%bb.10', '%bb.11' ]
body:             |
  ; MIPS32-LABEL: name: mod4_0_to_11
  ; MIPS32: bb.0.entry:
  ; MIPS32:   successors: %bb.6(0x40000000), %bb.1(0x40000000)
  ; MIPS32:   liveins: $a0
  ; MIPS32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
  ; MIPS32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
  ; MIPS32:   [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
  ; MIPS32:   [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
  ; MIPS32:   [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
  ; MIPS32:   [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
  ; MIPS32:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
  ; MIPS32:   [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
  ; MIPS32:   [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
  ; MIPS32:   [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
  ; MIPS32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
  ; MIPS32:   BNE [[ANDi]], $zero, %bb.6, implicit-def $at
  ; MIPS32: bb.1.entry:
  ; MIPS32:   successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
  ; MIPS32:   [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.0
  ; MIPS32:   [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
  ; MIPS32:   [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]]
  ; MIPS32:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
  ; MIPS32:   PseudoIndirectBranch [[LW]]
  ; MIPS32: bb.2.sw.bb:
  ; MIPS32:   $v0 = COPY [[ORi4]]
  ; MIPS32:   RetRA implicit $v0
  ; MIPS32: bb.3.sw.bb1:
  ; MIPS32:   $v0 = COPY [[ORi3]]
  ; MIPS32:   RetRA implicit $v0
  ; MIPS32: bb.4.sw.bb2:
  ; MIPS32:   $v0 = COPY [[ORi2]]
  ; MIPS32:   RetRA implicit $v0
  ; MIPS32: bb.5.sw.bb3:
  ; MIPS32:   $v0 = COPY [[ORi1]]
  ; MIPS32:   RetRA implicit $v0
  ; MIPS32: bb.6.sw.default:
  ; MIPS32:   successors: %bb.7(0x80000000)
  ; MIPS32: bb.7.sw.epilog:
  ; MIPS32:   successors: %bb.13(0x40000000), %bb.8(0x40000000)
  ; MIPS32:   [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
  ; MIPS32:   [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
  ; MIPS32:   [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
  ; MIPS32:   [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
  ; MIPS32:   BNE [[ANDi1]], $zero, %bb.13, implicit-def $at
  ; MIPS32: bb.8.sw.epilog:
  ; MIPS32:   successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
  ; MIPS32:   [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1
  ; MIPS32:   [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
  ; MIPS32:   [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi1]], [[SLL1]]
  ; MIPS32:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
  ; MIPS32:   PseudoIndirectBranch [[LW1]]
  ; MIPS32: bb.9.sw.bb4:
  ; MIPS32:   $v0 = COPY [[ORi4]]
  ; MIPS32:   RetRA implicit $v0
  ; MIPS32: bb.10.sw.bb5:
  ; MIPS32:   $v0 = COPY [[ORi3]]
  ; MIPS32:   RetRA implicit $v0
  ; MIPS32: bb.11.sw.bb6:
  ; MIPS32:   $v0 = COPY [[ORi2]]
  ; MIPS32:   RetRA implicit $v0
  ; MIPS32: bb.12.sw.bb7:
  ; MIPS32:   $v0 = COPY [[ORi1]]
  ; MIPS32:   RetRA implicit $v0
  ; MIPS32: bb.13.sw.default8:
  ; MIPS32:   $v0 = COPY [[ADDiu]]
  ; MIPS32:   RetRA implicit $v0
  ; MIPS32_PIC-LABEL: name: mod4_0_to_11
  ; MIPS32_PIC: bb.0.entry:
  ; MIPS32_PIC:   successors: %bb.6(0x40000000), %bb.1(0x40000000)
  ; MIPS32_PIC:   liveins: $a0, $t9, $v0
  ; MIPS32_PIC:   [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
  ; MIPS32_PIC:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
  ; MIPS32_PIC:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
  ; MIPS32_PIC:   [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
  ; MIPS32_PIC:   [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
  ; MIPS32_PIC:   [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
  ; MIPS32_PIC:   [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
  ; MIPS32_PIC:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
  ; MIPS32_PIC:   [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
  ; MIPS32_PIC:   [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
  ; MIPS32_PIC:   [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
  ; MIPS32_PIC:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
  ; MIPS32_PIC:   BNE [[ANDi]], $zero, %bb.6, implicit-def $at
  ; MIPS32_PIC: bb.1.entry:
  ; MIPS32_PIC:   successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
  ; MIPS32_PIC:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load (s32) from got)
  ; MIPS32_PIC:   [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
  ; MIPS32_PIC:   [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]]
  ; MIPS32_PIC:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
  ; MIPS32_PIC:   [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ADDu]]
  ; MIPS32_PIC:   PseudoIndirectBranch [[ADDu2]]
  ; MIPS32_PIC: bb.2.sw.bb:
  ; MIPS32_PIC:   $v0 = COPY [[ORi4]]
  ; MIPS32_PIC:   RetRA implicit $v0
  ; MIPS32_PIC: bb.3.sw.bb1:
  ; MIPS32_PIC:   $v0 = COPY [[ORi3]]
  ; MIPS32_PIC:   RetRA implicit $v0
  ; MIPS32_PIC: bb.4.sw.bb2:
  ; MIPS32_PIC:   $v0 = COPY [[ORi2]]
  ; MIPS32_PIC:   RetRA implicit $v0
  ; MIPS32_PIC: bb.5.sw.bb3:
  ; MIPS32_PIC:   $v0 = COPY [[ORi1]]
  ; MIPS32_PIC:   RetRA implicit $v0
  ; MIPS32_PIC: bb.6.sw.default:
  ; MIPS32_PIC:   successors: %bb.7(0x80000000)
  ; MIPS32_PIC: bb.7.sw.epilog:
  ; MIPS32_PIC:   successors: %bb.13(0x40000000), %bb.8(0x40000000)
  ; MIPS32_PIC:   [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
  ; MIPS32_PIC:   [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
  ; MIPS32_PIC:   [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
  ; MIPS32_PIC:   [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
  ; MIPS32_PIC:   BNE [[ANDi1]], $zero, %bb.13, implicit-def $at
  ; MIPS32_PIC: bb.8.sw.epilog:
  ; MIPS32_PIC:   successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
  ; MIPS32_PIC:   [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load (s32) from got)
  ; MIPS32_PIC:   [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
  ; MIPS32_PIC:   [[ADDu3:%[0-9]+]]:gpr32 = ADDu [[LW2]], [[SLL1]]
  ; MIPS32_PIC:   [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu3]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
  ; MIPS32_PIC:   [[ADDu4:%[0-9]+]]:gpr32 = ADDu [[LW3]], [[ADDu]]
  ; MIPS32_PIC:   PseudoIndirectBranch [[ADDu4]]
  ; MIPS32_PIC: bb.9.sw.bb4:
  ; MIPS32_PIC:   $v0 = COPY [[ORi4]]
  ; MIPS32_PIC:   RetRA implicit $v0
  ; MIPS32_PIC: bb.10.sw.bb5:
  ; MIPS32_PIC:   $v0 = COPY [[ORi3]]
  ; MIPS32_PIC:   RetRA implicit $v0
  ; MIPS32_PIC: bb.11.sw.bb6:
  ; MIPS32_PIC:   $v0 = COPY [[ORi2]]
  ; MIPS32_PIC:   RetRA implicit $v0
  ; MIPS32_PIC: bb.12.sw.bb7:
  ; MIPS32_PIC:   $v0 = COPY [[ORi1]]
  ; MIPS32_PIC:   RetRA implicit $v0
  ; MIPS32_PIC: bb.13.sw.default8:
  ; MIPS32_PIC:   $v0 = COPY [[ADDiu]]
  ; MIPS32_PIC:   RetRA implicit $v0
  bb.1.entry:
    liveins: $a0

    %0:gprb(s32) = COPY $a0
    %4:gprb(s32) = G_CONSTANT i32 7
    %8:gprb(s32) = G_CONSTANT i32 3
    %9:gprb(s32) = G_CONSTANT i32 2
    %10:gprb(s32) = G_CONSTANT i32 1
    %11:gprb(s32) = G_CONSTANT i32 0
    %18:gprb(s32) = G_CONSTANT i32 -1
    %1:gprb(s32) = G_CONSTANT i32 0
    %2:gprb(s32) = G_SUB %0, %1
    %3:gprb(s32) = COPY %2(s32)
    %5:gprb(s32) = COPY %4(s32)
    %22:gprb(s32) = G_ICMP intpred(ugt), %3(s32), %5
    %23:gprb(s32) = COPY %22(s32)
    %21:gprb(s32) = G_AND %23, %10
    G_BRCOND %21(s32), %bb.6

  bb.13.entry:
    successors: %bb.2, %bb.3, %bb.4, %bb.5

    %7:gprb(p0) = G_JUMP_TABLE %jump-table.0
    G_BRJT %7(p0), %jump-table.0, %3(s32)

  bb.2.sw.bb:
    $v0 = COPY %11(s32)
    RetRA implicit $v0

  bb.3.sw.bb1:
    $v0 = COPY %10(s32)
    RetRA implicit $v0

  bb.4.sw.bb2:
    $v0 = COPY %9(s32)
    RetRA implicit $v0

  bb.5.sw.bb3:
    $v0 = COPY %8(s32)
    RetRA implicit $v0

  bb.6.sw.default:

  bb.7.sw.epilog:
    %12:gprb(s32) = G_CONSTANT i32 8
    %13:gprb(s32) = G_SUB %0, %12
    %14:gprb(s32) = COPY %13(s32)
    %15:gprb(s32) = COPY %8(s32)
    %20:gprb(s32) = G_ICMP intpred(ugt), %14(s32), %15
    %24:gprb(s32) = G_CONSTANT i32 1
    %25:gprb(s32) = COPY %20(s32)
    %19:gprb(s32) = G_AND %25, %24
    G_BRCOND %19(s32), %bb.12

  bb.14.sw.epilog:
    successors: %bb.8, %bb.9, %bb.10, %bb.11

    %17:gprb(p0) = G_JUMP_TABLE %jump-table.1
    G_BRJT %17(p0), %jump-table.1, %14(s32)

  bb.8.sw.bb4:
    $v0 = COPY %11(s32)
    RetRA implicit $v0

  bb.9.sw.bb5:
    $v0 = COPY %10(s32)
    RetRA implicit $v0

  bb.10.sw.bb6:
    $v0 = COPY %9(s32)
    RetRA implicit $v0

  bb.11.sw.bb7:
    $v0 = COPY %8(s32)
    RetRA implicit $v0

  bb.12.sw.default8:
    $v0 = COPY %18(s32)
    RetRA implicit $v0

...
